research

Fault-tolerant quantum systems across QEC, compilers, and architecture.

Hardware-Aware Subsystem-Code Compilation

I currently work with Narayanan Rengaswamy on quantum error correction and subsystem-code compilation. We study how gauge freedom and equivalent logical realizations can be exposed algorithmically for scalable, hardware-aware synthesis. This matters because the same logical operation can admit very different physical costs, giving the compiler room to choose implementations that better match the hardware.

Hardware-Efficient qLDPC Codes

I currently work with Prakash Murali on hardware-efficient realizations of Bivariate Bicycle and Gross-family qLDPC codes. Our work uses algebraic equivalences to reshape code geometry and reduce connectivity overhead while preserving the underlying code structure. This matters because connectivity is one of the main barriers between attractive qLDPC code properties and practical fault-tolerant implementations.